[1]许 杰,张子恒,王新宇,等.一种基于 Zynq 的 CNN 加速器设计与实现[J].计算机技术与发展,2021,31(11):108-113.[doi:10. 3969 / j. issn. 1673-629X. 2021. 11. 018]
　XU Jie,ZHANG Zi-heng,WANG Xin-yu,et al.Design and Implementation of CNN Accelerator Based on Zynq[J].,2021,31(11):108-113.[doi:10. 3969 / j. issn. 1673-629X. 2021. 11. 018]
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一种基于 Zynq 的 CNN 加速器设计与实现()
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《计算机技术与发展》[ISSN:1006-6977/CN:61-1281/TN]

卷:
31
期数:
2021年11期
页码:
108-113
栏目:
系统工程
出版日期:
2021-11-10

文章信息/Info

Title:
Design and Implementation of CNN Accelerator Based on Zynq
文章编号:
1673-629X(2021)11-0108-06
作者:
许 杰; 张子恒; 王新宇; 佟 诚; 梅 青; 肖 建*
南京邮电大学 电子与光学工程学院、微电子学院,江苏 南京 210023
Author(s):
XU Jie; ZHANG Zi-heng; WANG Xin-yu; TONG Cheng; MEI Qing; XIAO Jian*
School of Electronic and Optical Engineering,School of Microelectronics,Nanjing University of Posts and Telecommunications,Nanjing 210023,China
关键词:
Zynq; 卷积神经网络; 硬件加速; 现场可编程逻辑门阵列; 数据量化; CIFAR-10
Keywords:
Zynq; convolutional neural network; hardware acceleration; FPGA; data quantification; CIFAR-10
分类号:
TP39
DOI:
10. 3969 / j. issn. 1673-629X. 2021. 11. 018
摘要:
卷积神经网络是一种前馈神经网络,它的人工神经元可以响应部分覆盖范围内的临近单元,对于大型图像处理有出色表现。 文中设计了一种基于 Zynq 芯片的 CNN 加速器,以期在资源和功耗受限的 FPGA 中实现运算性能加速。 该加速器采用数据量化的方式将网络参数从 64 位双精度浮点数转化为 16 位定点数;针对 CNN 不同层的特性和要求,设计了不同的网络结构和优化策略。 卷积层和全连接层采用循环分块、循环流水及循环展开等方法进一步改进,而池化层采用流水线的优化方式。 亦设计了 FPGA 和外部存储器的缓存策略,减少 FPGA 和外部存储器的数据传输量。 以 CIFAR-10 数据集下的图像识别为例,在 Zynq7020 实验平台上进行板级测试,实验结果表明,100 MHz 的工作频率下,平均识别时间为15. 5 ms,相对于单核 CPU 方案实现了 144 倍的加速。
Abstract:
Convolutional neural network is a feed-forward neural network whose artificial neurons can respond to neighboring units within partial coverage and perform well in large-scale image processing. A CNN accelerator based on the Zynq chip is designed to accelerate the computing perform-ance in the FPGA with limited resources and power consumption. The accelerator uses data quantization to quantify network parameters from? 64-bit double-precision floating-point numbers to 16-bit fixed-point numbers. According to the characteristics and requirements of different layers of CNN,different network structures and optimization strategies are designed. The convolutional layer and the fully connected layer are further improved by the methods of loop tiling,loop pipeline and loop unrolling,and the pooling layer uses the pipeline optimization method. A cache strategy for FPGA and external memory is designed to reduce the amount of data transfer between FPGA and external memory. Taking image recognition under the CIFAR-10 data set as an example,a board-level test was performed on the Zynq7020 experimental platform.The experiment shows that the average recognition time is 15. 5 ms at a working frequency of 100 MHz,which is 144 times faster than the single-core CPU solution.

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更新日期/Last Update: 2021-11-10