[1]杜 斐,何嘉文,王宣明,等.一种多核处理器芯片设计与实现关键技术研究[J].计算机技术与发展,2021,31(06):65-69.[doi:10. 3969 / j. issn. 1673-629X. 2021. 06. 012]
　DU Fei,HE Jia-wen,WANG Xuan-ming,et al.Research on Key Technology of Design and Implementation of a Multi-core Processor Chip[J].,2021,31(06):65-69.[doi:10. 3969 / j. issn. 1673-629X. 2021. 06. 012]
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一种多核处理器芯片设计与实现关键技术研究()

《计算机技术与发展》[ISSN:1006-6977/CN:61-1281/TN]

卷:
31
期数:
2021年06期
页码:
65-69
栏目:
系统工程
出版日期:
2021-06-10

文章信息/Info

Title:
Research on Key Technology of Design and Implementation of a Multi-core Processor Chip
文章编号:
1673-629X(2021)06-0065-05
作者:
杜 斐; 何嘉文; 王宣明; 蔡叶芳; 田 泽
航空工业西安航空计算技术研究所,陕西 西安 710068
Author(s):
DU Fei; HE Jia-wen; WANG Xuan-ming; CAI Ye-fang; TIAN Ze
AVIC Computing Technique Research Institute,Xi’an 710068,China
关键词:
异构多核处理器; 工作同步; 共享存储; FPGA 配置加载; 验证
Keywords:
heterogeneous multicore processor; synchronous work; shared storage; FPGA configuration load; validation
分类号:
TP39
DOI:
10. 3969 / j. issn. 1673-629X. 2021. 06. 012
摘要:
随着嵌入式技术的不断发展, HMPU 逐渐广泛应用于高性能计算领域。 异构多核处理器, 即具有两个或以上处理器内核的处理器,因其计算效率高,且可针对不同应用调整结构, 其应用相当广泛。在具体应用中, 多核处理器的不同处理器核之间需要进行大量的、频繁的数据交换,因此,处理器核间的通信效率严重影响处理器的性能。目前通过调查研究,异构多核处理器芯片核间通信领域已经在国内外取得了一些显著研究成果。 该文结合以上研究成果,针对电子系统数据与信号处理融合及 IO 综合管理需求,综合不同类型处理器的功能性能需求,以先进 SoC 为技术手段,基于国内现有IP 和自主工艺平台,在单芯片上实现数据处理及信号处理、多数据接口、高精度采集以及异构多核可定制信息处理为目的,提出一种基于“ CPU+DSP+FPGA+IO冶 结构的异构多核处理器芯片(heterogeneous multi-processor unit,HMPU) 的设计方案,采用共享总线的 Mailbox 异构多核间通信机制,以满足信号采样处理、总线协议处理、数据处理及控制功能。 重点阐述了 HMPU 的体系架构设计、详细设计及实现、虚拟仿真验证及 FPGA 原型验证等关键技术。 目前 HMPU 已经流片成功,并成功应用在多个领域。
Abstract:
With the development of embedded technology, HMPU is widely used in high performance computing. Heterogeneous multi core processors,that is,processors with two or more processor cores,are widely? ?used because of their high computational efficiency and the ability to adjust their structure for different applications. In practical applications,a large number of frequent data exchanges are needed between different cores of multi - core processors, so the efficiency of communication between cores seriously affects the performance of processors. At present,through investigation and research,some remarkable research achievements have been made in the field of inter-core communication of heterogeneous multi-core processor chips at home and abroad. Based on the above research results,for the requirements of data and signal processing integration of electronic system and IO integrated management, comprehensive functional performance requirements of different types of processors,we propose a design scheme of heterogeneous multi-core processor chip based on the structure of “CPU+DSP+FPGA+IO”with advanced SoC as the technical means,based on the domestic existing IP and independent technology platform, on the single chip to realize data processing and signal processing, data interface, high precision acquisition and more heterogeneous multi-core customizable information processing for the purpose. The shared bus mailbox communication mechanism between heterogeneous multi - core is adopted to meet the functions of the signal sampling processing, bus protocol processing,data processing and control. The key technolo-gies of HMPU architecture design,detailed design and implementation,virtual simulation verification and FPGA prototype verification are mainly described. At present,HMPU has been successfully streamed and applied in many fields.

相似文献/References:

[1]刘齐坚,王韦刚,高鹏程.基于GSLF-SSA的异构多核处理器任务调度[J].计算机技术与发展,2024,34(07):48.[doi:10.20165/j.cnki.ISSN1673-629X.2024.0121]
　LIU Qi-jian,WANG Wei-gang,GAO Peng-cheng.Task Scheduling for Heterogeneous Multi-core Processors Based on GSLF-SSA[J].,2024,34(06):48.[doi:10.20165/j.cnki.ISSN1673-629X.2024.0121]

更新日期/Last Update: 2021-06-10