[1]尹飞皓,尚建华.基于 ZYNQ 平台的图像处理算法 IP 验证系统研究[J].计算机技术与发展,2022,32(10):41-45.[doi:10. 3969 / j. issn. 1673-629X. 2022. 10. 007]
　YIN Fei-hao,SHANG Jian-hua.Research on IP Verification System of Image Processing Algorithm Based on ZYNQ Platform[J].,2022,32(10):41-45.[doi:10. 3969 / j. issn. 1673-629X. 2022. 10. 007]
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基于 ZYNQ 平台的图像处理算法 IP 验证系统研究()
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《计算机技术与发展》[ISSN:1006-6977/CN:61-1281/TN]

卷:
32
期数:
2022年10期
页码:
41-45
栏目:
媒体计算
出版日期:
2022-10-10

文章信息/Info

Title:
Research on IP Verification System of Image Processing Algorithm Based on ZYNQ Platform
文章编号:
1673-629X(2022)10-0041-05
作者:
尹飞皓; 尚建华
东华大学 信息科学与技术学院,上海 201620
Author(s):
YIN Fei-hao; SHANG Jian-hua
School of Information Science and Technology,Donghua University,Shanghai 201620,China
关键词:
图像处理; 视频传输; IP 验证系统; ZYNQ; 异构计算
Keywords:
image processing; video transmission; IP verification system; ZYNQ; heterogeneous computing
分类号:
TP391
DOI:
10. 3969 / j. issn. 1673-629X. 2022. 10. 007
摘要:
针对目前图像处理算法硬件验证平台成本高、验证环境不灵活、不易移植等问题,在 ZYNQ 异构计算平台上搭建了一套视频图像处理算法 IP(intellectual property) 验证系统,借助软硬协同手段进行系统开发,能够充分发挥 ZYNQ 平台的优势。 在处理系统侧部署嵌入式实时操作系统 FreeRTOS 并使用轻量级网络协议栈进行 TCP / IP 网络通信的开发,实现了图像数据的接收与发送;在可编程逻辑侧进行了图像算法的验证测试以及视频图像输出显示的控制。 通过自定义多个基于 AXI 总线协议的数据传输 IP 核以及对 ARM 端缓存的控制,完成了三次直接内存访问操作,实现了 ARM 端和 FPGA端的大数据高效互交。 最后,对两种不同的白平衡算法 IP 进行了验证。 测试验证结果表明,对于硬件资源开销较少的情况,该系统可以实现 400 Mbps 以上的视频传输速率,并且能够较好支持图像算法 IP 的验证,有效降低不必要的外设成本。
Abstract:
Aiming at the shortcomings of the current image processing algorithm hardware verification platform, such as high cost,inflexible verification environment and inconvenient transplantation, a video image processing algorithm IP ( intellectual property )verification system is developed on the ZYNQ heterogeneous computing platform by means of the software and hardware cooperation.The FreeRTOS operating system is implemented in the processing system and the lightweight network protocol stack ( LwIP) is used to improve the TCP / IP network communication to transmit image data. Besides,the image algorithm is tested and the image output display on the programmable logic side is controllable. By customizing multiple data transmission IP cores by AXI protocol and controlling the cache of ARM,the direct memory access and the big data interaction between ARM and FPGA are realized efficiently. Finally, two different white balance algorithms IP are verified. The experiment results show that the designed system can achieve a video transmission with the rate more than 400 Mbps. Mean while,it is a flexible support for the verification of image algorithm IP and is able to reduce unnecessary peripheral cost.

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更新日期/Last Update: 2022-10-10