[1]冯朝文,白 鹏,杨晓阔,等.混合忆阻器-CMOS 逻辑运算的优化设计研究[J].计算机技术与发展,2019,29(12):44-48.[doi:10. 3969 / j. issn. 1673-629X. 2019. 12. 008]
　FENG Chao-wen,BAI Peng,YANG Xiao-kuo,et al.Research on Optimization Design of Hybrid Memristor-CMOS Logic Operation[J].,2019,29(12):44-48.[doi:10. 3969 / j. issn. 1673-629X. 2019. 12. 008]
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混合忆阻器-CMOS 逻辑运算的优化设计研究()
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《计算机技术与发展》[ISSN:1006-6977/CN:61-1281/TN]

卷:
29
期数:
2019年12期
页码:
44-48
栏目:
智能、算法、系统工程
出版日期:
2019-12-10

文章信息/Info

Title:
Research on Optimization Design of Hybrid Memristor-CMOS Logic Operation
文章编号:
1673-629X(2019)12-0044-05
作者:
冯朝文; 白 鹏; 杨晓阔; 危 波
空军工程大学 基础部,陕西 西安 710051
Author(s):
FENG Chao-wen; BAI Peng; YANG Xiao-kuo; WEI Bo
Department of Basic Science,Air Force Engineering University,Xi’an 710051,China
关键词:
混合忆阻器-CMOS; 逻辑门; 信号衰减; 全加器; 暂态响应
Keywords:
hybrid Memristor-CMOS; logic gate; signal attenuation; full adder; transient response
分类号:
TN4
DOI:
10. 3969 / j. issn. 1673-629X. 2019. 12. 008
摘要:
基于混合忆阻器-CMOS 设计成的典型逻辑门在输出端的忆阻器存在泄露电流,导致运算输出信号幅度产生衰减,引起多级互联电路逻辑运算混乱甚至出错。 为了解决这一难题,文中提出采用变形逻辑运算表达式,以 CMOS 反相器可实现的“非”逻辑操作完成输出端信号传递这一方案,改进了电路运算设计结构但不改变电路运算的复杂度。 进而以“异或”、“异或非”逻辑门和一位全加器为例,以理论分析、新电路结构设计和 PSpice 软件模拟仿真三者共同验证了该方案的有效性。 研究结果表明,该方案很好地解决了级间连接忆阻器的泄露电流,有效降低了逻辑运算信号的衰减现象,且改进设计的电路逻辑功能正确,运算准确性得到提高,输出信号低电平近似为 0 V,高电平达 1.8 V,均接近理想值,有利于实现新型高性能复杂逻辑运算的设计、开发和大规模集成应用。
Abstract:
There is leakage current flowing through the memristors at the output end of typically designed logic gates designed with hybrid memristor–CMOS circuits,which results in the operational output signal attenuation and the multilevel interconnection logic operation confused or even wrong. In order to settle the problem,a new design scheme is proposed, which is that the transformed logical operation expression is used to complete the signal transmission at the output end by ‘NOT’ logical operation realized by CMOS inverter. The operation design structure of the circuit is improved without changing the circuit operation complexity and the attenuation of the outputsignal is effectively reduced. Then,taking ‘XOR’ ‘NXOR’ logic gates and one-bit full adder for example,the effectiveness of the seheme is verified by theoretical analysis,new circuit design and PSpice software simulation. The research shows that leakage current through the interstage memristors is restrained and logical operation signal attenuation is eliminated in this scheme. Also,the improved design circuits have correct logic function and high accuracy of logic operation with the low level of the output signal near 0 V and the high level up to 1.8 V,all of which are close to the ideal value. So,the scheme is beneficial to the design and development of new high-performance complex logic operations and large-scale integrated applications.
更新日期/Last Update: 2019-12-10