[1]邢艳芳,朱金付,周晓梅.基于Zynq 多核运行设计[J].计算机技术与发展,2018,28(03):60-62.[doi:10.3969/ j. issn.1673-629X.2018.03.012]
　XING Yan-fang,ZHU Jin-fu,ZHOU Xiao-mei.Design of Multi-core Processing Based on Zynq[J].,2018,28(03):60-62.[doi:10.3969/ j. issn.1673-629X.2018.03.012]
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基于Zynq 多核运行设计()
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《计算机技术与发展》[ISSN:1006-6977/CN:61-1281/TN]

卷:
28
期数:
2018年03期
页码:
60-62
栏目:
智能、算法、系统工程
出版日期:
2018-03-10

文章信息/Info

Title:
Design of Multi-core Processing Based on Zynq
文章编号:
1673-629X(2018)03-0060-03
作者:
邢艳芳1 ; 朱金付2 ; 周晓梅1
1. 中国传媒大学南广学院,江苏 南京 211172;
2. 东南大学,江苏 南京 210000
Author(s):
XING Yan-fang1 ; ZHU Jin-fu2 ; ZHOU Xiao-mei1
1. Nanguang College of Communication University of China,Nanjing 211172,China
2. Southeast University,Nanjing 210000,China
关键词:
Zynq; 非对称多核芯片; 共享内存; 片上内存; 主从关系
Keywords:
Zynq; asymmetric multiprocessing; shared memory; on-chip memory; master-slave relationship
分类号:
TP319
DOI:
10.3969/ j. issn.1673-629X.2018.03.012
文献标志码:
A
摘要:
多核处理器主要包括两种,即对称多核处理器(SMP)和非对称多核处理器(AMP)。 目前大部分通用多核处理器是 SMP,各个 CPU 是平等的,共享操作系统、内存和外设等资源;AMP 大多是嵌入式多核处理器采用的架构,由一个主 CPU控制系统运行和资源分配,从 CPU 执行主 CPU 的命令或者预定义任务。 Zynq 是 Xilinx 推出的全可编程芯片,是以 ARM为核心,以 FPGA 作为可编程外设的全新架构处理器。 Zynq 包括两个可以同时独立运行可执行程序的 Cortex-A9 处理器,是一种非对称多核芯片。 主处理器控制整个系统,从处理器执行主处理器的指令或者预定义任务,两个处理器是一种主
从关系。 文中 CPU0 是主处理器,控制系统和共享资源,CPU1 是从处理器,OCM 做 CPU0 和 CPU1 通信的共享内存。 实现了启动 Zynq 的双核 CPU,各自同时运行裸机程序,通过共享内存,实现了 CPU 之间的通信,并将运行信息在 OLED 上显示出来。
Abstract:
Multi-core processors mainly consists of two types,symmetrical multi-core processors (SMP) and asymmetric multi-core processors (AMP). At present most general multi-core processors are SMP which are equal among different CPUs,sharing the operating system,memory,peripherals and other resources. Most of AMP is the architecture adopted by the embedded multi-core processor,where a master CPU controls system operation and resources allocation,and the slave CPUs execute commands or predefined tasks from master CPU. Zynq is fully programmable chip launched by Xilinx recently,and is a processor with new architecture with ARM as its core and FPGA as its programmable peripheral. As an AMP,it includes two Cortex-A9 processors which can be configured to concurrently run independent software executables,in which a master processor controls the system,the slave processors execute the instruction or predefined tasks from the master processor,and it is a master-slave relationship between them. In this paper,CPU0 is treated as the master which conducts the system control and resources sharing,and CPU1 as the slave,and the on-chip memory (OCM) is used as shared memory for communication between CPU0 and CPU1. The startup of double-kernal CPU of Zynq is realized,and they run respective bare-metal program simultaneously. By sharing memory,the communication between CPUs is realized and the running information are displayed in
the organic light-emitting diode (OLED).

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更新日期/Last Update: 2018-04-08