[1]蔡叶芳,田泽,李攀,等. 一种RapidIO IP核的设计与验证[J].计算机技术与发展,2014,24(10):97-100.
　CAI Ye-fang,TIAN Ze,LI Pan,et al. Design and Implementation of a RapidIO IP Core[J].,2014,24(10):97-100.
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 一种RapidIO IP核的设计与验证()
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《计算机技术与发展》[ISSN:1006-6977/CN:61-1281/TN]

卷:
24
期数:
2014年10期
页码:
97-100
栏目:
智能、算法、系统工程
出版日期:
2014-10-10

文章信息/Info

Title:
 Design and Implementation of a RapidIO IP Core
文章编号:
1673-629X（2014）10-0097-04
作者:
 蔡叶芳; 田泽; 李攀; 何嘉文
 中国航空计算技术研究所
Author(s):
 CAI Ye-fang; TIAN Ze; LI Pan; HE Jia-wen
关键词:
 ; RapidIO; IP核设计; 验证方法
Keywords:
 ; RapidIO; IP core design; verification method
分类号:
TP39
文献标志码:
A
摘要:
 RapidIO总线是第三代总线的代表，是处理器之间实现互联的最佳选择。但国内对于此技术的研究尚处于起步阶段，使用者也多以购买国外成熟IP为主。文中基于RapidIO V1.3协议，介绍了一种RapidIO总线的设计和实现方法，之后对其进行了全面的虚拟平台测试和FPGA平台测试。测试结果表明，该RapidIO总线符合RapidIO V1.3协议，且设计实现方式简单，复用性好，可以作为RapidIO接口方便地应用于FPGA和芯片设计中。
Abstract:
 The RapidIO bus as one of the representatives of the third generation bus,is the best choice of the interconnection between pro-cessors. But in the domestic,the study of RapidIO bus is just begun,and the RapidIO IP is bought from outland mostly. Based on the Ra-pidIO V1. 3 protocol,describe a design and implementation method for the RapidIO bus,and has carried on the comprehensive test in vir-tual platform and FPGA platform. The simulation result shows that,this design meets the RapidIO V1. 3 protocol,and is simple to imple-ment,has good reusability,and can be easily used in the design of FPGA and chip as RapidIO interface.

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更新日期/Last Update: 2015-04-02