[1]李现坤,张瑛,郭宇锋,等. 一种10 bit 1 MS/s SAR ADC的设计实现[J].计算机技术与发展,2014,24(08):210-214.
　LI Xian-kun,ZHANG Ying,GUO Yu-feng,et al. Design and Implementation of a 10 bit 1 MS/s SAR ADC[J].,2014,24(08):210-214.
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 一种10 bit 1 MS/s SAR ADC的设计实现()
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《计算机技术与发展》[ISSN:1006-6977/CN:61-1281/TN]

卷:
24
期数:
2014年08期
页码:
210-214
栏目:
应用开发研究
出版日期:
2014-08-10

文章信息/Info

Title:
 Design and Implementation of a 10 bit 1 MS/s SAR ADC
文章编号:
1673-629X（2014）08-0210-05
作者:
 李现坤; 张瑛; 郭宇锋; 杨恒新
 南京邮电大学 电子科学与工程学院
Author(s):
 LI Xian-kun; ZHANG Ying; GUO Yu-feng; YANG Heng-xin
关键词:
 ; 数模转换器; 逐次逼近寄存器; 比较器; 失调误差
Keywords:
 ; Analog to Digital Converter (ADC); Successive Approximation Register (SAR); compactor; offset voltage
分类号:
TN432
文献标志码:
A
摘要:
 基于0.13μm CMOS工艺,设计了一种采样率达到1 MS/s的10位逐次逼近模数转换器,其中逐次逼近数字控制逻辑采用全定制的方法,减小了数字单元的面积和功耗；比较器中的预放大器分别采用了二极管连接和开关管复位的方式将各级运放的输出短接,加快比较速度,最后一级锁存器采用改进的两级动态锁存器,进一步提升比较速度的同时降低了失调误差。实验结果表明,1.2 V电源电压下,所设计的ADC采样率达到1 MS/s,输入信号频率为12.5 kHz时,测得的输出信号信噪比为54.47 dB,SFDR为45.18 dB。
Abstract:
 On the basis of 0. 13 μm CMOS process,a 10-bit,1 MS/s Successive Approximation Register Analog-to-Digital Converter ( SAR ADC) is presented. The successive approximation control logic is designed by the method of full customization,which can achieve the smaller area and lower power compared with logic synthesis. During the compactor design,diode-connected MOS transistors and reset switch are used as short-circuit plug to bridge the outputs of every pre-amplifier respectively,and it accelerates the comparison speed. An improved two-stage dynamic latch is applied at the end of latch stage,which further increases comparison speed and reduces the offset voltage. At a 1. 2-V supply,the sampling rate is high up to 1 MS/s with 12. 5 kHz sinusoidal input. The simulated SNR and SFDR are 54. 47 dB and 45. 18 dB respectively.

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更新日期/Last Update: 2015-03-31