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《计算机技术与发展》[ISSN:1006-6977/CN:61-1281/TN]

卷:

24

期数:

2014年05期

页码:

117-119

栏目:

智能、算法、系统工程

出版日期:

2014-05-31

文章信息/Info

Title:

FPGA Prototype Verification Method for IEEE1394 Physical Layer IP

文章编号:

1673-629X（2014）05-0117-03

作者:

王治; 田泽; 黎小玉; 徐文进

中国航空计算技术研究所

Author(s):

WANG Zhi; TIAN Ze; LI Xiao-yu; XU Wen-jin

关键词:

IEEE1394; PHY; 原型验证; Serdes

Keywords:

IEEE1394; PHY; prototype verification; Serdes

分类号:

TP301

文献标志码:

A

摘要:

符合IEEE1394协议的物理层IP主要完成总线连接检测、连接管理、仲裁、数据收发等功能,是一款集成高速Ser-des的数模混合SoC。由于在Serdes的测试芯片设计完成前无法对1394物理层IP进行全面验证,因此文中在介绍1394 PHY物理层IP各部分功能的基础上,提出了一种以Xilinx的GTP代替1394物理层Serdes,构建FPGA原型验证平台,采用专用硬件逻辑和软件结合的方式,对1394物理层IP进行充分验证的方法。使用该平台可在Serdes设计未完成前对数字逻辑进行验证,大大缩短物理层IP的开发周期；通过软件控制下的测试项生成、测试过程监控、测试结果判断,可显著提高验证效率。

Abstract:

According to the protocol,IEEE1394 PHY IP mainly implements the function of bus interconnection,connection management, bus arbitration,data transmission and so on. It is a kind of digital and analog mixed SoC integrated a high-speed Serdes. As it is hard to fully verify 1394 PHY IP before the Serdes chip is designed,therefore based on introduction of the 1394 PHY IP function,put forward a kind of method to meet the need for PHY IP verification,including using GTP of Xilinx FPGA instead of Serdes,constructing FPGA pro-totype verification platform,adopting hardwire logic work along with software to make verification works. Applying the platform can veri-fy the digital logic before the Serdes is completed,greatly shortening the development time of physics layer IP. Through the test items generation,test processing monitor,test result judgment under software control,can remarkably improve the verification efficiency.

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更新日期/Last Update: 1900-01-01