电能计量芯片 Sigma-Delta ADC降采样滤波器设计-《计算机技术与发展》

文章信息/Info

Title:: Decimation Filter Design of Electrical Energy Measurement IC Sigma-Delta ADC

Keywords:: Sigma-Delta ADC; decimation filter; cascaded integrator comb filter; half band filter; compensation filter

摘要:: Sigma-Delta ADC 精度高,是电能计量芯片的首选 ADC.文中设计了一个应用于电能计量芯片中∑-△ADC 的数字抽取滤波器,将∑-△调制器输出的串行比特流信号转换成多位并行输出.该抽取滤波器采样多级抽取结构,由级联积分梳状滤波器(Cascaded Integrator Comb,CIC),半带滤波器(Half Band Filter, HBF)以及 FIR 补偿滤波器组成.对各级滤波器的阶数、系数进行优秀设计,实现128倍的抽取.对 HBF 采用有符号正则数编码节(CSD)编码,经优化设计后,在CSMC 0.18um 工艺下综合,与传统方法相比,面积减少8%,功耗降低15%.实验结果表明:该方法使抽取滤波器在面积和功耗上都有所改善,且性能完全符合电能计量芯片设计要求

Abstract:: Electrical energy measurement requires high accuracy,Sigma-Delta ADC meets it. It presents a decimator filter that can be used in electrical energy measurement IC for ∑-△ADC,using this decimation will converted the Sigma-Delta modulator signal of the serial bit stream into a number of parallel. The filter consists of a CIC filter,a HBF and a FIR compensation filter. Optimize the order and coef-ficient to realize decimation ratio of 128. In implemention of HBF with CSD code,use CSMC 0. 18um process to synthesis and then found the area is less than 8% ,and power dissipation is less than 15% ,compared with convention method after optimization. Experimental re-sults show the decimation filter has improved in the area and power,and performance in full compliance with the requirements of the ener-gy metering chip