[1]王玉欢 田泽 蔡叶芳.RapidIO IP核的验证方法研究[J].计算机技术与发展,2011,(07):183-185.
　WANG Yu-huan,TIAN Ze,CAI Ye-fang.Verification Method Research for RapidIO IP Core[J].,2011,(07):183-185.
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RapidIO IP核的验证方法研究()
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《计算机技术与发展》[ISSN:1006-6977/CN:61-1281/TN]

卷:
期数:
2011年07期
页码:
183-185
栏目:
应用开发研究
出版日期:
1900-01-01

文章信息/Info

Title:
Verification Method Research for RapidIO IP Core
文章编号:
1673-629X（2011）07-0183-03
作者:
王玉欢 田泽 蔡叶芳
中国航空计算技术研究所
Author(s):
WANG Yu-huan; TIAN Ze; CAI Ye-fang
Aeronautical Computing Technique Research Institute
关键词:
RapidIO; IP核; 验证平台; 验证
Keywords:
RapidIO IP core;  testbench;  verification
分类号:
TP39
文献标志码:
A
摘要:
串行RapidIO是针对高性能嵌入式系统芯片间和板间互连而设计的,是未来十几年中嵌入式系统互连的最佳选择之一。在以RapidIO为接口的SoC设计中,对RapidIO IP核的验证是其基础。基于对RapidIO协议的理解,研究了RapidIO IP核功能验证的方法、验证平台的搭建以及验证测试过程的实施,提出了虚拟平台验证与FPGA原型验证相结合的验证方法。该验证过程搭建了可靠的验证平台,为RapidIO IP核的可靠工作提供了保证。文中的研究工作,从验证思路和方法上对于类似设计的验证具有一定的参考价值
Abstract:
Serial RapidIO is designed for the connection among chips of high performance embedded system and that among boards.It is one of the best choices for the interconnection of embedded system in the future.In the SoC design with the RapidIO as its interface,verification for RapidIO core is the foundation.Based on the understanding of RapidIO protocol,take a research of the method of RapidIO core functional verification,the foundation of verification terrace and the implementation of the verification test process,raised the verification method that combined the virtual terrace verification and FPGA archetype verification.This verification process found a dependable verification testbench,guaranteeing the dependable work of RapidIO IP core.For similar designed verification,research in this essay has some reference value in mentality and method field of verification

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备注/Memo

备注/Memo:
中国航空工业集团公司技术创新基金（2009D63120）王玉欢（1984-），女，陕西西安人，硕士，助理工程师，主要从事数字集成电路设计和验证等方面的研究；田泽，博士，研究员，研究方向为SoC设计、嵌入式系统设计、VLSI设计等
更新日期/Last Update: 1900-01-01