[1]张波,韩俊刚. 基于SDSoC的SIFT特征点检测[J].计算机技术与发展,2016,26(12):103-106.
　ZHANG Bo,HAN Jun-gang. Scale Invariant Feature Transform Algorithm Based on SDSoC[J].,2016,26(12):103-106.
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 基于SDSoC的SIFT特征点检测()
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《计算机技术与发展》[ISSN:1006-6977/CN:61-1281/TN]

卷:
26
期数:
2016年12期
页码:
103-106
栏目:
智能、算法、系统工程
出版日期:
2016-12-10

文章信息/Info

Title:
 Scale Invariant Feature Transform Algorithm Based on SDSoC
文章编号:
1673-629X（2016)12-0103-04
作者:
 张波; 韩俊刚
 西安邮电大学 计算机学院
Author(s):
 ZHANG Bo; HAN Jun-gang
关键词:
 ; SIFT; SDSoC; 软硬件协同; FPGA
Keywords:
 ; SIFT; SDSoC; co-design of software and hardware; FPGA
分类号:
TP391
文献标志码:
A
摘要:
 为了在嵌入式机器视觉处理系统中能够快速提取图像的特征点，完成图像匹配与物体识别等操作，提出了一种在全可编程器件上实现的SIFT( Scale Invariant Feature Transform)算法。该算法使用SDSoC开发环境，采用PS( Processing Sys-tem)和PL( Programmable Logic)协同开发策略，通过流水线优化、软硬件并行和重构算法顺序等方法对算法进行优化。对多幅QVGA分辨率图像进行了处理，结果表明软硬件协同开发的策略能够有效提高算法性能，同时能保留较多特征点。该算法生成的特征点在尺度变换、旋转和缩放的情况下均能得到良好的匹配效果。与现有使用软件实现的SIFT方案相比，具有一定的实时性，满足了在嵌入式领域的应用需求。
Abstract:
 In order to extract image feature points in embedded machine vision system quickly and complete operations such as image matching and object recognition,a SIFT ( Scale Invariant Feature Transform) algorithm is put forward on an all programmable device. It uses SDSoC environment and PS ( Processing System) and PL ( Programmable Logic) co-design strategy,and is optimized through the pipeline optimization,parallel hardware and software and reconstruction of algorithm sequence. Images of QVGA resolution are pro-cessed,and the results show that the methodology of hardware and software co-design can effectively improve performance of SIFT algo-rithm,while retaining many feature points. This algorithm generates the feature points to match well under the condition of the scale trans-form,rotation and scaling. Compared with the existing implementation of SIFT by software,the performance of real-time meets the appli-cation requirements in the embedded field.

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更新日期/Last Update: 2017-02-03