[1]李姝萱,卜 刚,韩宇昕.基于 UVM 的软硬件协同验证平台设计[J].计算机技术与发展,2022,32(08):76-81.[doi:10. 3969 / j. issn. 1673-629X. 2022. 08. 013]
　LI Shu-xuan,BU Gang,HAN Yu-xin.Design of UVM-based Software and Hardware Co-simulation Verification Platform[J].,2022,32(08):76-81.[doi:10. 3969 / j. issn. 1673-629X. 2022. 08. 013]
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基于 UVM 的软硬件协同验证平台设计()
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《计算机技术与发展》[ISSN:1006-6977/CN:61-1281/TN]

卷:
32
期数:
2022年08期
页码:
76-81
栏目:
系统工程
出版日期:
2022-08-10

文章信息/Info

Title:
Design of UVM-based Software and Hardware Co-simulation Verification Platform
文章编号:
1673-629X(2022)08-0076-06
作者:
李姝萱; 卜 刚; 韩宇昕
南京航空航天大学 电子信息工程学院,江苏 南京 211106
Author(s):
LI Shu-xuan; BU Gang; HAN Yu-xin
School of Electronic Information Engineering,Nanjing University of Aeronautics and Astronautics,Nanjing 211106,China
关键词:
通用验证方法学; 软硬件协同验证; 串口; 现场可编程门阵列; 覆盖率驱动
Keywords:
universal verification methodology ( UVM) ;  hardware and software co - verification;  serial port;  field - programmable gatearray ( FPGA) ; coverage-driven
分类号:
TP33
DOI:
10. 3969 / j. issn. 1673-629X. 2022. 08. 013
摘要:
随着芯片的规模和复杂度日益增大,软件环境下的功能验证越来越无法满足高效率的芯片生产流程的需求。 因此,验证效率的提高变得十分关键。 针对 RFID 数字基带系统中标签———阅读器链路的 FM0 和 Miller 编码模块,利用FPGA 硬件平台的高速性能和面向对象编程的优势,搭建了一种基于覆盖率驱动的 UVM 软硬件协同验证平台。 FPGA 端将集成有 RS-232 串口收发模块的可综合待测设计下载到硬件上,PC 端采用 winsock API 编写数据上行和下行通路的 C程序。 验证平台仍保留在仿真软件 QuestaSim 中运行,并通过 DPI 接口调用的方式与硬件平台进行通信。 最终,上述方案在 Altera 开发板实现。 实验结果表明,该验证平台的功能覆盖率达到 100% ,能够有效提高验证效率并且能够为大规模SoC 的验证所用,同时还具有硬件资源占用率低以及可维护性和可复用性强的优点。
Abstract:
With the increasing size and complexity of chips,functional verification in a software environment is increasingly unable tomeet the needs of high - efficiency chip production processes. Therefore,? the improvement of verification efficiency becomes critical.Aiming at the FM0 and Miller encoding modules of the tag-reader link in the RFID ( Radio Frequency Identification) digital basebandsystem,a coverage-driven hardware and software co-verification platform based on UVM ( Universal Verification Methodology) is implemented by utilizing the high-speed performance of the FPGA hardware and the advantages of OOP ( Object Oriented Programming) .The design to be verified integrated with RS - 232 serial port transceiver module is downloaded to the FPGA hardware, while the PCterminal writes the C programs for the data uplink and downlink channels with winsock API. The verification platform still runs in the simulation software QuestaSim and communicates with the hardware with the DPI interface. Finally, the above - mentioned projectimplemented with Altera development board. Experimental results show that the functional coverage of the verification platform reached100% ,which can effectively improve the simulation efficiency and can be reusable for the verification of large-scale SoC. It also has theadvantages of low hardware resource occupancy,strong maintainability and reusability.

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更新日期/Last Update: 2022-08-10