异构紧耦合可重构密码芯片关键技术研究-《计算机技术与发展》

文章信息/Info

Title:: Research on Key Techniques of Heterogeneous Tightly Coupled Reconfigurable Cipher Chip

Author(s):: CUI Guang-cai; SHI Yi-juan; MENG Tao; Jiangnan Institute of Computing Technology,Wuxi 214000,China

Keywords:: heterogeneous coupled; reconfigurable cipher; cipher chip; FPGA; ASIC; chip design

摘要:: 在大数据时代,不管是数据密集型的应用,还是以数据为驱动的 AI 应用,对算力的要求越来越高。随着超大规模集成电路和可重构计算技术的快速发展,对可重构密码芯片设计技术进行了研究,报告了当前可重构密码芯片的发展现状,针对可重构密码芯片的高性能与高灵活性应用需求,结合细粒度 FPGA 和粗粒度 ASIC 两种硬件架构的优势,提出了异构紧耦合的可重构密码芯片架构。基于该架构,给出了异构紧耦合的可重构密码芯片设计模型,利用 FPGA 实现灵活的控制逻辑,利用 ASIC 实现高速的密码运算,通过紧耦合的接口设计提高整体的处理性能。仿真结果表明,基于 FPGA+ ASIC的异构紧耦合可重构密码芯片,既可以实现较高的处理性能,又能灵活实现多种密码算法,可提供不同级别的数据安全保护能力。

Abstract:: In the era of big data, the requirements for computing power are getting higher and higher whether it is data-intensive applications or data-driven AI applications. With the rapid development of VLSI and reconfigurable computing technology, the design technology of reconfigur-
able cipher chips is researched,and the development status of current reconfigurable cipher chips is reported. Aimed at the application requirements of high performance and high flexi-bility of reconfigurable cipher chips, combined with the advantages of fine-grained FPGA and coarse-grained ASIC hardware architecture,a heterogeneous tightly coupled reconfigurable cipher chip architecture is proposed. Based on the architecture,a design model of heterogeneous tightly coupled reconfigurable chip is presented, in which the flexible control logic is realized by FPGA, the high-speed cryptographic operation is realized by ASIC, and the overall processing performance is improved by tightly coupled interface design. The simulation shows that the FPGA + ASIC-based heterogeneous tightly coupled reconfigurable cipher chip can achieve high processing performance and flexible implementation of multiple cryptographic algorithms,providing different levels of the ability of data security protection.