[1]陈正博,吴铁彬,郑 方,等.面向人工智能的浮点乘加器设计[J].计算机技术与发展,2019,29(08):96-101.[doi:10. 3969 / j. issn. 1673-629X. 2019. 08. 019]
　CHEN Zheng-bo,WU Tie-bin,ZHENG Fang,et al.Design of Floating Point Multiply-Adder for Artificial Intelligence[J].,2019,29(08):96-101.[doi:10. 3969 / j. issn. 1673-629X. 2019. 08. 019]
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面向人工智能的浮点乘加器设计()
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《计算机技术与发展》[ISSN:1006-6977/CN:61-1281/TN]

卷:
29
期数:
2019年08期
页码:
96-101
栏目:
智能、算法、系统工程
出版日期:
2019-08-10

文章信息/Info

Title:
Design of Floating Point Multiply-Adder for Artificial Intelligence
文章编号:
1673-629X(2019)08-0096-06
作者:
陈正博; 吴铁彬; 郑 方; 丁亚军
江南计算技术研究所,江苏 无锡 214000
Author(s):
CHEN Zheng-bo; WU Tie-bin; ZHENG Fang; DING Ya-jun
Jiangnan Institute of Computing Technology,Wuxi 214000,China
关键词:
人工智能; 浮点乘加器; 单精度; 半精度; 单半混合精度
Keywords:
artificial intelligence; floating point multiplicator; single precision; half precision; single-half-mixed precision
分类号:
TP302
DOI:
10. 3969 / j. issn. 1673-629X. 2019. 08. 019
摘要:
近年来,面向人工智能领域的芯片快速发展,低精度和混合精度的乘加运算能力是人工智能芯片计算能力的核心指标,同时乘加部件也是人工智能芯片功率的主要消费者。 面向人工智能领域应用需求,研究高性能、低能耗、低开销的浮点乘加器,对人工智能芯片的研发具有重要意义。 文中设计了一种面向 AI 的浮点乘加器,支持单精度、半精度、单半混合精度的浮点乘加运算,也支持 32 位、16 位和 8 位的整数乘法运算。 该部件采用跨精度复用的设计思想,提出乘法器复用、移位器复用、前导零预测器复用等关键技术,在保证各类操作功能和性能的基础上,有效减少了芯片面积和功耗。 文中完成了该部件的正确性测试和物理综合。 实验结果表明,该部件能满足正确性要求,在 28 nm 工艺条件下,对比无复用设计至少减少 50.09%的面积和 47.91%的功耗,综合运行频率达到 2 GHz。
Abstract:
In recent years,chips in the field of artificial intelligence have been developing rapidly. The multiply-add operation with low precision and mixed precision is the core index of the computing power of artificial intelligence chips,and the multiply-add components are also the main consumers of the power of artificial intelligence chips. It is of great significance for the research and development of artificial intelligence chips to study floating point multiplicator with high performance,low energy consumption and low overhead for the application demand in the field of artificial intelligence. In this paper,an AI-oriented floating point multiplicator is designed,which supports the floating point multiplication and addition operations with single precision,half precision and single-half-mixed precision,as well as the integer multiplication operations with 32,16 and 8 bits. This design adopts the idea of cross-precision reuse and reduces the area and power of chips with ensuring all kind of operation functions and performance,by using proposed key technology like multiplier-reuse,shifter-reuse,LZA-reuse. We finish the correctness test and physical syntheses. The experiment shows that this architecture is correct in all operations. Compared with the no-reuse design,at least 50. 09% of the area and 47.91% of the power consumption can be reduced under the condition of 28 nm process. The comprehensive operating frequency can reach 2 GHz.

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更新日期/Last Update: 2019-08-10