[1]谢晓燕,芦守鹏,邓军勇,等.移动GPU中模型视图变换单元的可重构设计[J].计算机技术与发展,2019,29(01):55-60.[doi:10. 3969 / j. issn. 1673-629X. 2019. 01. 012]
　XIE Xiao-yan,LU Shou-peng,DENG Jun-yong,et al.Reconfigurable Design of Model View Transformation Unit inMobile GPU[J].,2019,29(01):55-60.[doi:10. 3969 / j. issn. 1673-629X. 2019. 01. 012]
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移动GPU中模型视图变换单元的可重构设计()
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《计算机技术与发展》[ISSN:1006-6977/CN:61-1281/TN]

卷:
29
期数:
2019年01期
页码:
55-60
栏目:
智能、算法、系统工程
出版日期:
2019-01-10

文章信息/Info

Title:
Reconfigurable Design of Model View Transformation Unit inMobile GPU
文章编号:
1673-629X(2019)01-0055-06
作者:
谢晓燕;  芦守鹏;  邓军勇;  田汝佳
西安邮电大学 计算机学院,陕西 西安,710061;西安邮电大学 电子工程学院,陕西 西安,710061
Author(s):
XIE Xiao-yan1; LU Shou-peng1; DENG Jun-yong2; TIAN Ru-jia2
1. School of Computer Science and Technology,Xi’an University of Posts and Telecommunications,Xi’an 710061,China;2. School of Electronic Engineering,Xi’an University of Posts and Telecommunications,Xi’an 710061,China
关键词:
模型视图变换;  可重构;  并行计算;  移动图形处理器;  矩阵计算
Keywords:
model view transformation; reconfigurable; parallel computing; mobile graphics processors; matrix computations
分类号:
TP302
DOI:
10. 3969 / j. issn. 1673-629X. 2019. 01. 012
文献标志码:
A
摘要:
针对移动图形处理器,正确显示并渲染图像是一个重要的指标,尤其是在保证图像质量的基础上,如何在多个PE(processing element)阵列的结构上将图像变换时的矩阵计算并行化,并在低功耗和有限带宽的情况下实现高效的图形渲染和高质量的图形效果是一项十分重要的工作.结合图形学中的3 D仿射变换的基本概念和过程,并根据PE阵列结构的算法映射特点,提出一种可重构模型视图变换单元的并行化设计方案.该方案使用32个PE对平移、缩放、旋转操作的矩阵运算进行并行处理,并在FPGA(field programmable gate array)开发板上完成了原型验证.FPGA平台的输出结果和Linux平台的输出结果对比表明,可重构电路可以正确实现预期的图形变换效果.这种设计方案更具有灵活性且可以实时适应计算任务要求的变化,其电路工作频率可达183.23 MHz.
Abstract:
For the mobile GPU,displaying and rendering the image correctly is an important indicator. Especially on the basis of ensuringthe image quality,how to parallelize the matrix computation of image transformation in the structure of multiple PE and achieve efficientrendering and high quality graphics effect under the condition of low power consumption and limited bandwidth is an important work.Combined with the basic concept of 3D affine transformation in computer graphics and the algorithm mapping characteristics of PE arraystructure,we propose a parallelized design scheme of reconfigurable model view transformation unit. The scheme uses 32 PEs to parallelize the matrix computation of translation,scaling and rotation operations,and complete the prototype verification on the FPGA board. Thecomparison between the output image of FPGA platform and the output image of Linux platform shows that the reconfigurable circuit canachieve the expected effect of graphics transformation. This design is more flexible and can adapt to changes in computing tasks requirements,the circuit frequency can reach 183. 23 MHz
更新日期/Last Update: 2019-01-10