[1]曹朋朋,田泽,赵强,等. SoC芯片中SRIO接口的FPGA验证平台设计验证[J].计算机技术与发展,2016,26(06):183-185.
　CAO Peng-peng,TIAN Ze,ZHAO Qiang,et al. Design and Verification of SRIO in SoC Based on FPGA[J].,2016,26(06):183-185.
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 SoC芯片中SRIO接口的FPGA验证平台设计验证()
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《计算机技术与发展》[ISSN:1006-6977/CN:61-1281/TN]

卷:
26
期数:
2016年06期
页码:
183-185
栏目:
应用开发研究
出版日期:
2016-06-10

文章信息/Info

Title:
 Design and Verification of SRIO in SoC Based on FPGA
文章编号:
1673-629X（2016)06-0183-03
作者:
 曹朋朋; 田泽; 赵强; 李攀; 王泉
 西安航空计算技术研究所 集成电路与微系统设计航空科技重点实验室
Author(s):
 CAO Peng-peng; TIAN Ze; ZHAO Qiang; LI Pan; WANG Quan
关键词:
 ; SRIO; FPGA平台; 设计 ; 验证
Keywords:
 ; SRIO; FPGA platform; design; verification
分类号:
TP39
文献标志码:
A
摘要:
 SRIO接口基于串行包交换协议,包含SRIO接口的高性能处理器已广泛应用于航空嵌入式系统中,SRIO高速接口功能与性能的验证是整个系统设计的关键,设计可靠完备的验证平台对芯片SRIO接口的验证至关重要。文中基于对Ra-pidIO协议的理解,基于一款SoC芯片设计并搭建了FPGA验证平台,策划FPGA功能验证点,完成对SRIO核的验证。基于文中的验证平台可完成SRIO接口不同线速率,不同线宽,以及SRIO不同包类型的覆盖验证,测试内容已覆盖SRIO协议中规定的内容。
Abstract:
 SRIO interface is based on serial packet switch protocol. High-performance embedded CPU with SRIO interface is widely used in avionics embedded system. The verification of SRIO interface is particularly important for the design of the system. A reliable and com-plete verification platform for SRIO interface is very important. Based on the understanding of RapidIO protocol in this paper,a FPGA verification platform is designed and implemented based on SoC,planing functional test point and accomplishing the verification of SRIO IP core. The verification platform described in this paper can test SRIO interface with different line rates,different line width,and different package types. The content of the test has been covered by the SRIO protocol.

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更新日期/Last Update: 2016-09-26