[1]廖寅龙,田泽,赵强,等. PCIe总线物理层弹性缓冲设计与实现[J].计算机技术与发展,2016,26(06):168-170.
　LIAO Yin-long,TIAN Ze,ZHAO Qiang,et al. Design and Implementation of PCIe Physical Layer Elastic-buffer[J].,2016,26(06):168-170.
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 PCIe总线物理层弹性缓冲设计与实现()
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《计算机技术与发展》[ISSN:1006-6977/CN:61-1281/TN]

卷:
26
期数:
2016年06期
页码:
168-170
栏目:
应用开发研究
出版日期:
2016-06-10

文章信息/Info

Title:
 Design and Implementation of PCIe Physical Layer Elastic-buffer
文章编号:
1673-629X（2016)06-0168-03
作者:
 廖寅龙; 田泽; 赵强; 马超
 西安航空计算技术研究所 集成电路与微系统设计航空科技重点实验室
Author(s):
 LIAO Yin-long; TIAN Ze; ZHAO Qiang; MA Chao
关键词:
 ; PCIe ; 弹性缓冲; 同步FIFO; 半满
Keywords:
 ; PCIe; elastic-buffer; synchronous-FIFO; half-full
分类号:
TP39
文献标志码:
A
摘要:
 PCIe是在PCI总线的基础上提出的新一代总线和接口标准，它原来的名称为“3GIO”，是由英特尔在2001年提出的。 PCIe属于高速串行点对点双通道高带宽传输，所连接的设备分配独享通道带宽，不共享总线带宽，主要支持主动电源管理、错误报告、端对端的可靠性传输、热插拔以及服务质量( QOS)等功能。 PCIe作为高速串行数据总线以其众多的优点在计算机、通讯、航空航天等领域得到了广泛应用。为了实现稳定可靠的数据通讯，必须解决总线恢复时钟域数据和本地时钟域数据的同步问题，弹性缓冲区是实现PCIe总线接口数据同步机制的有效方法。文中根据PCIe协议要求，分析PCIe总线通信中时钟偏差的多种场景，设计了一款采用20位数据总线，读写时钟频率可达250 MHz的弹性缓冲，有效解决了PCIe总线通信中总线恢复时钟域与本地时钟域的数据同步问题。
Abstract:
 PCIe is a new generation of bus and interface based on PCI bus,its original name is"3GIO",was introduced by Intel in 2001. PCIe belongs to dual channel high bandwidth transmission of high speed serial point to point,the connected equipment allocates unshared bandwidth of channel that do not share bus bandwidth,mainly supporting the functions including active power management,bug reports, end to end transmission of the reliability,hot swappable and Quality of Service ( QoS) etc. PCIe had been widely applied in computer, communication,aeronautics and astronautics and other fields as the high-speed-serial data bus. In order to realize stable and reliable com-munication,elastic-buffer is considered as necessary in PCIe which is used to ensure data integrity between the recovered clock domain and the local clock domain. It analyzes the clock-skew under the variable scenes based on PCIe specification and designs a kind of elastic-buffer with 20 bits data bus and 250 MHz R/W clock frequency,solving the problem of data synchronization between bus recovery clock domain and local clock domain.

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更新日期/Last Update: 2016-09-26