[1]王晋,田泽,唐龙飞. 1.2 V7 bits 125 Mb/s双采样流水线模数转换器[J].计算机技术与发展,2015,25(07):206-208.
　WANG Jin,TIAN Ze,TANG Long-fei. Design of Double Sample 1 . 2 V 7 bits 125 Mb/s Pipelined ADC[J].,2015,25(07):206-208.
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 1.2 V7 bits 125 Mb/s双采样流水线模数转换器()
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《计算机技术与发展》[ISSN:1006-6977/CN:61-1281/TN]

卷:
25
期数:
2015年07期
页码:
206-208
栏目:
应用开发研究
出版日期:
2015-07-10

文章信息/Info

Title:
 Design of Double Sample 1 . 2 V 7 bits 125 Mb/s Pipelined ADC
文章编号:
1673-629X（2015)07-0206-03
作者:
 王晋; 田泽; 唐龙飞
 中国航空计算技术研究所
Author(s):
 WANG Jin；TIAN Ze；TANG Long-fei
关键词:
 ; 双采样; 流水线; ADC采样率
Keywords:
 ; double sample; pipeline; ADC sampling
分类号:
TP31
文献标志码:
A
摘要:
 为了满足SoC系统对低功耗和高性能模数转换器ADC的需求,文中设计了一种双采样1.2 V 7位125 Mb/s流水线模数转换器。该双采样流水线模数转换器是由两个转换通道组成,两个转换通道之间采用时钟交织技术。为了减小整个模数转换器的功耗和面积,同时消除采样时序失配问题,文中提出了一种在两个通道之间共用运算放大器的电路结构以及相应的工作时序关系。该模数转换器采用0.13-μm CMOS 1p8m工艺实现。仿真结果表明,该模数转换器的最大SNDR为43.38 dB,有效位数ENOB为6.8位。在电源电压为1.2 V,采样速率为125 Mb/s时,该模数转换器的功耗为10.8 mW。
Abstract:
 A 7 bits 125 Mb/s double sample pipelined ADC which can achieve low power and high performance for SoC system is presen-ted. The double sampling pipelined ADC is consisted of two conversion channel,the clock mixed technology is used between two conver-sion channel. In order to reduce power consumption and area of the entire ADC,eliminate the sampling timing mismatch problems at the same time,put forward an operational amplifier circuit structure and the corresponding work timing relationships shared between the two channels. Simulation results show that the ADC designed in a 0. 13-μm CMOS process achieves a maximum SNDR of 43. 38 dB,and ENOB is 6. 8 bits. The ADC consumes 10. 8 mW at 125 Mb/s under a 1. 2-V supply voltage.

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更新日期/Last Update: 2015-09-08