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《计算机技术与发展》[ISSN:1006-6977/CN:61-1281/TN]

卷:

24

期数:

2014年05期

页码:

1-4

栏目:

智能、算法、系统工程

出版日期:

2014-05-31

文章信息/Info

Title:

Research on Timing Constraint of Static Timing Analysis Based on H. 264/AVC Decoder

文章编号:

1673-629X（2014）05-0001-04

作者:

刘宁宁; 田泽; 郭蒙

中国航空计算技术研究所

Author(s):

LIU Ning-ning; TIAN Ze; GUO Meng

关键词:

解码芯片; 静态时序分析; 约束

Keywords:

decoder; STA; constraint

分类号:

TP39

文献标志码:

A

摘要:

作为分析和验证电路时序行为的重要手段，静态时序分析( STA)技术在深亚微米级ASIC设计中得到了广泛的应用，而正确的时序约束输入是时序分析工具给出正确结果的必要条件之一。文中在介绍 STA 原理的基础上，以一款H.264/AVC解码芯片为例，分析了解码芯片的时钟结构等时序信息，详细介绍了时钟定义、端口信号等关键时序约束，并重点介绍了PLL时钟偏差的约束设计。时序分析工具PT分析及与动态仿真的交叉验证的结果表明，解码芯片时序约束设计完整、正确。

Abstract:

As an important method of timing analysis and check,Static Timing Analysis ( STA) has been used more and more widely in Nano-scale process. A proper constraint is a necessary condition of precise STA report to be given. In this paper,based on introducing the basic principle of STA,analyze the timing structure and other temporal information of decoder,a critical timing constraints are introduced in detail with the H. 264/AVC as the instance,such as clock definition and port signal,and the clock latency of PLL is stressed. The result of PT and cross-verification with post-sim shows that the constraint design is integrated and correct.

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更新日期/Last Update: 1900-01-01