[1]郭蒙,田泽,胡小婷,等.数字集成电路多周期路径的设计实现方法[J].计算机技术与发展,2013,(08):204-206.
 GUO Meng,TIAN Ze,HU Xiao-ting,et al.Implementation of Multi-cycle Path in Digital IC Design[J].,2013,(08):204-206.
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数字集成电路多周期路径的设计实现方法()
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《计算机技术与发展》[ISSN:1006-6977/CN:61-1281/TN]

卷:
期数:
2013年08期
页码:
204-206
栏目:
应用开发研究
出版日期:
1900-01-01

文章信息/Info

Title:
Implementation of Multi-cycle Path in Digital IC Design
文章编号:
1673-629X(2013)08-0204-03
作者:
郭蒙田泽胡小婷廖寅龙
中国航空计算技术研究所
Author(s):
GUO MengTIAN ZeHU Xiao-tingLIAO Yin-long
关键词:
多周期路径数字集成电路静态时序分析时序电路
Keywords:
多周期路径数字集成电路静态时序分析时序电路
文献标志码:
A
摘要:
多周期路径是将复杂电路运算拆分在多个时钟周期完成,从而提高电路总体运行频率的一种设计方法,是数字电路中广泛使用的一种设计手段。实践中多周期路径的设计、约束与实现经常误用导致设计迭代和反复。文中结合在研项目,对多周期路径的产生机理进行了系统的分析,针对设计中常见的问题展开分析,提出了一种多周期路径的设计实现和施加约束的方法。实践结果表明,采用文中提供的方法可以有效避免多周期路径的误用,减少设计迭代,提高设计效率
Abstract:
Multi-cycle path is the data path which needs multiple clock cycle to complete computation in the circuit. Multi-cycle path is widely used in digital integrated circuit design to improve the operating frequency of the circuit. However,it is frequently found design it-eration as the result of multi-cycle path being misused in design practice. By the research and analysis of multi-cycle path in IC design and problems often found during design process,a way of multi-cycle path implementing and constraint is presented. The result shows that this method avoids the misuse of multi-cycle path efficiently,improves design efficiency and shortens the whole design process

相似文献/References:

[1]左航 金玉丰.一种基于Vera的集成电路建模验证方法[J].计算机技术与发展,2007,(01):94.
 ZUO Hang,JIN Yu-feng.A Vera Modeling Verification Method in Integrated Circuit[J].,2007,(08):94.

更新日期/Last Update: 1900-01-01